A look at the latest CPUs

Modern CPUs chase higher throughput per watt with wider superscalar cores, deeper out‑of‑order machinery, smarter caches, and specialized accelerators — then scale out with hybrid cores and chiplets.

What changed since “classic” cores?

• From multi‑socket → multi‑core on a single package
• Aggressive superscalar front‑ends (wide fetch/decode, large µop cache)
• Deeper OoO windows, larger load/store queues, more execution ports
• Per‑core power gating + turbo logic managed by an on‑die controller
• On‑chip memory controller; NUMA appears in multi‑socket/chiplet designs

<aside> ⚙️

IPC levers

• Wider decode/dispatch (up to ~32 instr/cycle claimed)
• µop cache ≈ 4K entries to skip decode on hot code
• ≥12 exec ports; bigger ROB and LSQs (>100)
• Better branch prediction and prefetching </aside>

Caches (fast SRAM)

• L1/L2 per core, shared L3; L2 now ~1–2 MB common
• Smarter prefetching: stride prefetch (L1), predictive line‑write (L2)
• Locality still rules: scattered accesses hurt performance

Simultaneous Multithreading (Hyper‑Threading)

• 1 core ⇒ 2 logical threads sharing backend resources
• Typical gains: 15–30% for latency‑bound mixes; not a substitute for extra cores
• Some new parts drop HT to trade area/power for more E‑cores