CPU Pipeline and Branch Prediction

📑 Navigation

What is a CPU Pipeline? • Pipeline Stages • Pipeline as Assembly Line • Instructions Per Clock (IPC) • Pipeline Stalls • RISC vs CISC • Branch Prediction Introduction • Branch Prediction Techniques • Loop Buffers • Complex Branch Predictors • Branch Predictor Unit Architecture • Impact of Branch Prediction • Key Takeaways

What is a CPU Pipeline?

Definition

A CPU pipeline breaks instruction execution into separate stages, allowing multiple instructions to be processed simultaneously at different stages.

Key insight: Instead of completing one instruction entirely before starting the next, the CPU works on multiple instructions concurrently, each at a different stage of completion.

Why Pipelining?

Early computers executed instructions sequentially:

• Fetch instruction (maybe 10+ clock cycles)
• Decode instruction (several cycles)
• Execute instruction (variable cycles)
• Write back results (several cycles)

Problem: This approach wasted time. While decoding one instruction, the fetch unit sat idle.

Solution: Pipeline the stages so each stage works continuously on different instructions.

Real-World Analogy

Think of a car factory assembly line:

Station 1: Install wheels
Station 2: Spray paint
Station 3: Install interior
Station 4: Final inspection

You wouldn't:

• Build entire car at Station 1