Superscalar Architecture

Course: Computer Systems I (COMP1313)

Topics: Superscalar execution, Instruction-level parallelism, Out-of-order execution, Register renaming, Dependencies

What is Superscalar?

Goal: Complete more than one instruction per clock cycle

Recall from last lecture:

• We achieved 1 IPC (1 instruction per clock) through pipelining
• Today we're going to beat that and finish 2, 3, 4+ instructions per clock cycle

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Why Superscalar? Moore's Law is slowing down. We can't increase clock speeds much beyond 4-5 GHz, so instead we finish more instructions per clock cycle to get faster performance.

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Etymology: Why "Superscalar"?

• Scalar operations = work on individual values (not vectors/arrays)
• Superscalar = performing multiple scalar operations simultaneously
• Aim: Complete more than one instruction per clock cycle

Simple Example:

c = a + b;  // Instruction 1
d = e * f;  // Instruction 2

These two instructions use different variables and different operations. If the CPU has the hardware, it can execute both simultaneously!

CPU Architecture for Superscalar

Functional Units